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2-4

Mixed-Port Read-During-Write Mode

SV51003

2013.05.06

Figure 2-2: Same-Port Read-During-Write: New Data Mode

This figure shows sample functional waveforms of same-port read-during-write behavior in the “ new data ”

mode.

clk_a

address

rden

wren

byteena

0A

11

0B

data_a

q_a (asynch)

A123

A123

B456

B456

C789

C789

DDDD

DDDD

EEEE

EEEE

FFFF

FFFF

Mixed-Port Read-During-Write Mode

The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports

perform read and write operations on the same memory address using the same clock — one port reading

from the address, and the other port writing to it.

Table 2-3: Output Modes for RAM in Mixed-Port Read-During-Write Mode

Output Mode

"new data"

"old data"

"don't care"

Altera Corporation

Memory Type

MLAB

M20K, MLAB

M20K, MLAB

Description

A read-during-write operation to different ports causes the

MLAB registered output to reflect the “ new data ” on the

next rising edge after the data is written to the MLAB

memory.

This mode is available only if the output is registered.

A read-during-write operation to different ports causes the

RAM output to reflect the “ old data ” value at the particular

address.

For MLAB, this mode is available only if the output is

registered.

The RAM outputs “ don ’ t care ” or “ unknown ” value.

? For M20K memory, the Quartus II software does not

analyze the timing between write and read operations.

? For MLAB, the Quartus II software analyzes the timing

between write and read operations by default. To disable

this behavior, turn on the Do not analyze the timing

between write and read operation. Metastability issues

are prevented by never writing and reading at the

same address at the same time option.

Embedded Memory Blocks in Stratix V Devices

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